Apparatus and method to provide a single reference component for multiple circuit compensation using digital impedance code shifting

ABSTRACT

A single external impedance element is used to perform multiple circuit compensation. A reference impedance code is first generated based on matching an internal impedance generated by transistors with an impedance of the external impedance element, and then the reference impedance code can be shifted to generate new impedance codes according to impedance requirements of various different circuits that require compensation. Use of the single external impedance element for compensation of multiple circuits reduces motherboard and packaging costs. Chip area is also conserved since simpler compensation circuits can be used.

TECHNICAL FIELD

[0001] This disclosure relates generally to electronic devices, and inparticular but not exclusively, relates to use of a single referencecomponent to provide multiple circuit compensation by using digitalimpedance code shifting.

BACKGROUND

[0002] Because high-frequency processors are becoming more sensitive tovariations in process, supply voltage, and temperature (P-V-T), itbecomes prudent to compensate critical circuits for these variations.For example, on-die termination circuits, input/output (I/O) pre-drivercircuits, timing control circuits, etc. are compensated because theyaffect overshoots, undershoots, signal reflections, timing control(Tco), and signal edge rates. Comparing a resistance of an externalresistor to the resistance of an internal compensation circuit is thebasis for compensating these critical circuits. Accordingly, for eachkind of circuit (e.g., on-die termination circuit, I/O pre-drivercircuit, Tco circuit, etc.), a separate external resistor is used tocompensate each of the required circuit attributes (such as impedance,slew rate, and timing).

[0003]FIG. 1 is a schematic diagram of a circuit compensation techniquethat uses multiple external resistors. The technique shown in FIG. 1compensates a critical circuit across P-V-T by using an externalresistor R (shown in FIG. 1 as having an example value of 100 Ohms) tomatch a resistance of a compensation circuit 10 formed on a chip 12. Thecompensation circuit 10 comprises a plurality of P-channel metal oxidesemiconductor (PMOS) transistors, referred to as “transistor legs.” Inthe example of FIG. 1, there are 32 transistor legs.

[0004] Matching the on-chip internal resistance of the compensationcircuit 10 to the resistance of the external resistor R is done byhaving a first finite state machine FSM1 turn on the transistor legs oneat a time until the effective on-chip internal resistance isapproximately equal to the resistance of the external resistor R. Atthis moment, a comparator circuit 14 (coupled to the external resistorR, to the compensation circuit 10, and to a voltage supply Vdd) trips,and the number of activated transistor legs in the compensation circuit10 is recorded by the finite state machine FSM1.

[0005] From this number of activated transistor legs, a digitalimpedance code is generated by the finite, state machine FSM1 thatrepresents the matched on-chip internal resistance. The finite statemachine FSM1 then provides this impedance code (representing 100 Ohms inthe example) to other compensation circuits, such as to other Tcocircuits on the chip 12 if the compensation circuit 10 compensated fortiming, so that these other compensation circuits can compensate thatsame circuit attribute.

[0006] However, if many different circuits need to be compensated acrossP-V-T for different circuit attributes, a separate impedance code needsto be generated for each circuit. Thus in FIG. 1, n circuits to becompensated require n external resistors Rx. As is often the case, theresistance of any one of the external resistors Rx (40 Ohms as anexample in FIG. 1) needs to be different than the resistance of theexternal resistor R or the resistances of other external resistors.

[0007] As apparent in FIG. 1, compensation of many different circuitsrequires many additional internal resistors (e.g., additionalcompensation circuits 16), finite state machines FSMn, comparatorcircuits 18, etc. The addition of these redundant on-chip componentsincreases fabrication costs and consumes valuable real estate on thechip 12. The use of multiple external resistors R to Rx increasespackaging costs and motherboard costs, since multiple pads (e.g., pad 1to pad n) or pins must be provided, respectively, for the externalresistors R to Rx.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Non-limiting and non-exhaustive embodiments of the presentinvention are described with reference to the following figures, whereinlike reference numerals refer to like parts throughout the various viewsunless otherwise specified.

[0009]FIG. 1 is a schematic diagram of a circuit compensation techniquethat uses multiple external resistors.

[0010]FIG. 2 is a schematic diagram of a circuit compensation techniquein accordance with an embodiment of the invention that uses a singleexternal resistor.

[0011]FIG. 3 is a table illustrating an example embodiment of impedancecode shifting for the circuit compensation technique of FIG. 2.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

[0012] Embodiments of a method and apparatus to provide a singlereference component for multiple circuit compensation, via use ofimpedance code shifting, are described herein. In the followingdescription, numerous specific details are given, such as specificimpedance values in FIGS. 2 and 3, to provide a thorough understandingof embodiments of the invention. One skilled in the relevant art willrecognize, however, that the invention can be practiced without one ormore of the specific details, or with other methods, components,materials, values, etc. In other instances, well-known structures,materials, or operations are not shown or described in detail to avoidobscuring aspects of the invention.

[0013] Reference throughout this specification to “one embodiment” or“an embodiment” means that a particular feature, structure, orcharacteristic described in connection with the embodiment is includedin at least one embodiment of the present invention. Thus, theappearances of the phrases “in one embodiment” or “in an embodiment” invarious places throughout this specification are not necessarily allreferring to the same embodiment. Furthermore, the particular features,structures, or characteristics may be combined in any suitable manner inone or more embodiments.

[0014] As an overview, an embodiment of the invention provides a morecost-effective technique for multiple circuit compensation usingimpedance code shifting, such as digital impedance code shifting. Asingle reference component, in the form of a single reference impedancecode corresponding to an internal resistance substantially matched to aresistance of a single external resistor, is used to compensate multipleand different circuit attributes. That is, in an embodiment, the singleexternal resistor is used to compensate various circuits (or circuitattributes) by digitally shifting the reference impedance code accordingto the impedance requirements of each circuit to be compensated.

[0015] Packaging costs are decreased since only one extra pin or padneed be used for compensation purposes, as compared to multiple pads forthe compensation technique of FIG. 1. Motherboards cost are alsodecreased since only one external resistor need be used forcompensation. An embodiment of the compensation technique alsosimplifies the circuits used for compensation, and thus results inreduction of chip area usage.

[0016]FIG. 2 is a schematic diagram of a circuit compensation techniquein accordance with an embodiment of the invention that uses a signalexternal resistor or other single external impedance element Z. Theimpedance element Z may be mounted on a motherboard 20. For purposes ofillustration and explanation, the impedance element Z will be describedherein as having a resistance of 51 Ohms. It is to be appreciated thatthis resistance value is merely an example and may be different in otherembodiments. For the sake of discussion, the 51-Ohm resistance of theimpedance element Z can be associated with an on-die termination circuitfor a uni-processor system, although it may be associated with otherdifferent types of circuits, such as I/O pre-driver circuits, Tcocircuits, on-die termination circuits for multi-processor systems, orother circuits.

[0017] A chip 22 is mounted on or otherwise coupled to the motherboard20. At least one compensation circuit 24 is formed on the chip 22. In anembodiment, the compensation circuit 24 comprises a plurality ofimpedance-generation devices, shown in FIG. 2 as a plurality of PMOStransistors or transistor legs. For the sake of illustration, 32transistor legs w1-w32 are shown in the embodiment of FIG. 2. It is tobe appreciated that other compensation circuits on the chip 22 or otherembodiments can have any number of transistor legs. Moreover, while theembodiment shown in FIG. 2 uses PMOS transistors in the compensationcircuit 24, other embodiments or other compensation circuits on the chip22 can be implemented with N-channel metal oxide semiconductor (NMOS)transistors. In such NMOS implementations, a person skilled in the arthaving the benefit of this disclosure can re-configure the compensationcircuit 24 so that the NMOS transistors are connected asimpedance-generation devices. In yet another embodiment, a combinationof NMOS and PMOS transistors may be present in the compensation circuit24.

[0018] Source terminals of the transistor legs w1-w32 are coupled to avoltage source Vdd. Their drain terminals are coupled to the externalimpedance element Z by or at a pad 26. Their gate terminals are coupledby a bus 30 to a control circuit 32, which will be described laterbelow. In the example of FIG. 2, there are 32 lines in the bus 30,corresponding to each of the transistor legs w1-w32.

[0019] The transistor legs w1-w32 can be associated to or correspond toa circuit attribute, such as on-die termination, I/O pre-driverstrength, timing control slew rate, signal edge rate control, or othercircuit attribute that can be compensated. For purposes of discussionherein, the transistor legs w1-w32 will be associated to compensationfor the on-die termination circuit attribute for a uni-processor system.

[0020] A comparator circuit 34 is coupled to the impedance element Z andto the plurality of PMOS transistors in the compensation circuit 24. Anoutput terminal 36 of the comparator circuit 34 is coupled to thecontrol circuit 32, which in one embodiment includes a finite statemachine FSM. An embodiment of the control circuit 32 also includes acounter 38 (such as an up/down counter). The counter 38 is coupled tothe output terminal 36 of the comparator circuit 34, and is also coupledto the gate terminals of the PMOS transistors in the compensationcircuit 24 via the bus 30.

[0021] In operation, the control circuit 32 first generates a referenceimpedance code. This is done by having the control circuit 32 activatethe transistor legs w1-w32 one at a time until the impedance (orconductance) of the activated transistor legs substantially matches theresistance/impedance of the external impedance element Z, which in thisexample is 51 Ohms. Once there is a substantial match of impedances, thecomparator circuit 34 trips and provides a signal at its output terminal36 to the control circuit 32. The signal from the comparator circuit 34causes the control circuit 32 to read the value in the counter 38, whichin this case has recorded the number of transistor legs that areactivated to match 51 Ohms. In an embodiment, the number provided by thecounter 38 is a digital or binary number that the finite state machineFSM (or other component of the control circuit 32) designates orotherwise produces as the reference impedance code that corresponds,tothe impedance of the activated transistor legs.

[0022] Once the reference impedance code is generated, the finite statemachine FSM shifts the reference impedance code up or down to generateother impedance codes to compensate for other different circuitattributes. Examples of amounts of these shifts to compensate othercircuit attributes for illustrative purposes include, but are notlimited to, an upward shift of 18 to compensate on-die termination for adual-processor system to 8 Ohms, a downward shift of −4 to compensateedge rate control to 78 Ohms, a downward shift of −12 to compensate forI/O timing control (Tco) to 180 Ohms, and so on. This shifting of thereference impedance code is shown generally at 40 in FIG. 2.

[0023] The control circuit 32 has a plurality of output terminals toprovide the various values of the shifted reference impedance code(which now are in effect new impedance codes) to other compensationcircuits 42-48 corresponding to other different circuit attributes. Inaccordance with an embodiment of the invention, the counter 38 can atleast partly control activation or deactivation of individualimpedance-generation devices in these other compensation circuits basedon the amount of the shift of the reference impedance code. Therefore,for example, if the impedance code for 8 Ohms is to be provided to thecompensation circuit 42, then the counter 38 counts up (e.g., shifts orincrements) the value of the reference impedance code by 18. This newimpedance code is provided by the control circuit 32, via lines (shownin FIG. 2 as comprising 5 lines, as an illustration, to the compensationcircuit 42), to gate terminals of impedance-generation devices of thecompensation circuit 42. In response, at least one impedance-generationdevice of the compensation circuit 42 is activated to providecompensation impedance that corresponds to the received impedance code.

[0024] Thus, an embodiment of the invention need utilize only the singleexternal impedance element Z and only a single control circuit 32 (andhence only the single finite state machine FSM and the single comparatorcircuit 34) for multiple circuit compensation. It is to be appreciated,however, that in other embodiments where motherboard costs, packagingcosts, and chip area are less of a concern, additional numbers of thesecomponents may be used for multiple circuit. compensation.

[0025] It is noted that the embodiment of the compensation circuit 24shown in FIG. 2 is an example that is based on p-device dependence.Stated in another way, all similar p-devices in similar circuits willturn on the same number of p-devices. Thus, if compensation for aparticular on-die termination circuit requires 5 activated p-devices forthe proper impedance, all other on-die termination circuits on the samechip 22 will also be compensated by having 5 of their associatedp-devices activated. In other embodiments, n-device dependence may beused, or less or no device dependence may be used.

[0026] In an embodiment of the invention, the PMOS transistors in thecompensation circuit 24 (as well as in other compensation circuits 42-48on the chip 22) have variable physical widths. These variable widthsprovide the PMOS transistors with different individual impedances whenthey are activated. Hence, by designing the total number of PMOStransistors present in each compensation circuit 24 and by selecting thewidths of the individual transistors, a range of impedances can be madeavailable and the change in impedance for each shift can becalculated/designed.

[0027] The width of each transistor leg in one embodiment can becalculated as W_(n)=W_(n−1)+y * W_(n−1), where y is the incrementalwidth from one transistor leg to the next transistor leg and where n=1for the starting width for the first transistor leg. For the specificembodiment shown in FIG. 2 for the PMOS transistors in the compensationcircuit 24 or for the compensation circuits 42-48, n is between [2,32]since 32 PMOS transistors are present.

[0028] W_(n) is the total width of the n transistor legs turned on. Theresistance/impedance is generally inversely proportional to W_(n), suchthat as the number of transistor legs that are turned on increase, thetotal impedance decreases. The total impedance or resistance can begenerally stated as R_(n)≈K/W_(n), where K=L/(U_(n)C_(ox)V_(eff)). Inthis equation, L is the length, U_(n) is the mobility, C_(ox) is thegate oxide capacitance, and V_(eff) is the gate-to-source voltage V_(GS)minus the threshold voltage V_(t) for the transistor legs.

[0029] The incremental width y (e.g., “step”) from one transistor toanother can be 10% (e.g., y=0.1), and it is to be appreciated that y canbe a greater or lesser percentage based on the desired amount ofprecision. For instance, if y is a smaller percentage (including nochange in width for PMOS transistors of uniform widths) then shiftingfrom one set of turned-on PMOS transistor legs to another set of PMOStransistor legs results in a smaller change in impedance, and hence moreprecise impedance adjustment. In such a case, more PMOS transistors maybe formed on the chip 22 if a greater range for the total impedance isdesired. Conversely, if y is made larger, shifting from one set ofturned-on PMOS transistor legs to another set of PMOS transistor legsresults in greater impedance changes.

[0030] Thus, the PMOS transistors in one embodiment have differentwidths that correspond to a different impedance that can be generated byeach PMOS transistor. A shift in the reference impedance code by thecontrol circuit 32 results in activation or deactivation of PMOStransistors in any one of the compensation circuits 42-48 to generatedifferent impedances based on an amount of the shift.

[0031]FIG. 3 is a table 50 that illustrates an embodiment of impedancecode shifting for the compensation technique of FIG. 2. Specifically,the table 50. has entries for the total resistance R_(n), the transistorlegs w1-w32, the amount of shifting for the reference impedance code,and the circuit types (or circuit attributes) to be compensated, and soon that are consistent with what is shown in FIG. 2. For the table ofFIG. 3, y has a value of 0.1 for purposes of discussion, meaning thatthe PMOS transistors in the compensation circuit 24 have a step increasein width of 10% relative to a width of a previous adjacent PMOStransistor. Hence, the resistance R_(n) decreases by 10% as the PMOStransistors are activated one at a time. It is understood that theentries in the table 50 are merely for explanation and are notnecessarily intended to fully reflect actual circuit conditions.

[0032] The table 50 identifies the transistor legs w1-w32 at 52. Thewidth(s) W_(n) of the activated PMOS transistors are indicated at 54,which may have values in microns. The total resistance R_(n) for theactivated transistors is indicated at 56. Hence, the resistance of thefirst activated PMOS transistor can be 200 Ohms. The resistance of thefirst and second activated PMOS transistors is thus 200 Ohms minus(0.1)(200 Ohms)=180 Ohms. The remaining values of the total resistanceR_(n) up to the transistor leg w32 can be roughly calculated for thetable 50 using this methodology. Examples of various different circuits(or different circuit attributes) to be compensated are shown at 58.

[0033] The reference impedance code, corresponding to 51 Ohms in FIG. 2,is shown in the table 50 as corresponding to 14 activated PMOStransistors (e.g., the transistor legs w1 to w14) for compensation ofon-die termination (Rtt) for a uni-processor system. If it is known(from design simulation or via other testing technique) thatcompensation for on-die termination Rtt for a dual-processor system willrequire 8 Ohms and hence 32 activated transistor legs, the referenceimpedance code corresponding to 51 Ohms (14 activated transistor legs)is shifted upward (e.g., to the right in the table 50 by adding 18 tothe reference impedance code) to generate a new impedance code toactivate the transistor legs w1 to w32.

[0034] For downward shifting to obtain a higher resistance, such as tocompensate for edge rate control at 78 Ohms, the reference impedancecode is shifted to the left (e.g., the reference impedance code issubtracted by 4) so that a new impedance code to activate the transistorlegs w1 to w10 is generated. For obtaining an even greater compensationresistance, such as for I/O timing control at 180 Ohms, the referenceimpedance code is shifted to the left (e.g., the reference impedancecode is subtracted by 12) such that an impedance code to. activate thetransistor legs w1 and w2 is generated. Thus, via reference codeshifting, the required compensation impedance codes for other circuitsare obtained.

[0035] In an embodiment, multiple circuit compensation may be performedon a regular basis, so that circuit compensation can be continuouslyupdated. This updating can involve monitoring circuit conditions, andthen repeating the shifting of the reference impedance code andrepeating the using of the shifted reference impedance code to activateor deactivate at least one or more PMOS transistor legs in a particularcompensation circuit. This repeating can thus be performed in responseto a change in state of a circuit attribute, such as a change due toP-V-T for impedance, slew rate, timing control, and the like, todeactivate or activate impedance-generation devices in any of thecompensation circuits identified above.

[0036] Referring again to FIG. 2, the control circuit 32 may becontrolled by instructions (such as software or other machine readablecode) to perform the various shifting, PMOS transistoractivation/deactivation, or other operations described above, inresponse to a state of a particular circuit attribute. Such instructionsmay be stored on a machine-readable medium 60 coupled to or mounted onthe motherboard 20 (or on the chip 22). In one embodiment, theseinstructions can be executed by a processor 62. Both the processor 62and the machine-readable medium 60 can be connected to each other and tocomponents on the chip 22 via a bus 64. In an embodiment, the multiplecircuit compensation described above can be performed as part of a basicinput/output system (BIOS) routine during startup, or may be performedat other times by other routines.

[0037] In conclusion, an embodiment of the invention uses the singleexternal impedance element Z to perform multiple circuit compensation. Areference impedance code is first generated, and then the referenceimpedance code can be incremented or decremented (e.g., shifted) togenerate new impedance codes according to impedance requirements ofvarious different circuits that require compensation. Using the singleexternal impedance element for compensation of multiple circuits reducesmotherboard and packaging costs. Furthermore, chip area is alsoconserved since simpler compensation circuits can be used.

[0038] The above description of illustrated embodiments of the inventionincluding what is described in the Abstract, is not intended to beexhaustive or to limit the invention to the precise forms disclosed.While specific embodiments of, and examples for, the invention aredescribed herein for illustrative purposes, various equivalentmodifications are possible within the scope of the invention, as thoseskilled in the relevant art will recognize.

[0039] These modifications can be made to the invention in light of theabove detailed description. The terms used in the following claimsshould not be construed to limit the invention to the specificembodiments disclosed in the specification and the claims. Rather, thescope of the invention is to be determined entirely by the followingclaims, which are to be construed in accordance with establisheddoctrines of claim interpretation.

What is claimed is:
 1. An apparatus, comprising: a single externalimpedance element having an impedance; a plurality ofimpedance-generation devices coupled to the single external impedanceelement, the plurality of impedance-generation devices corresponding toa circuit attribute; and a control circuit coupled to the plurality ofimpedance-generation devices, the control circuit capable to activate atleast one device of the plurality of impedance-generation devices togenerate an impedance that substantially matches the impedance of thesingle external impedance element to compensate the circuit attributeand capable to produce a reference impedance code corresponding to thegenerated impedance the control circuit further capable to shift thereference impedance code to activate or deactivate at least one deviceof another plurality of impedance-generation devices to generate anotherimpedance to compensate a different circuit attribute.
 2. The apparatusof claim 1 wherein the external impedance element comprises a resistor.3. The apparatus of claim 1 wherein the plurality ofimpedance-generation devices comprises P-channel transistors.
 4. Theapparatus of claim 1 wherein the plurality of impedance-generationdevices comprises N-channel transistors or a combination of P-channeltransistors and N-channel transistors.
 5. The apparatus of claim 1wherein the control circuit comprises a finite state machine.
 6. Theapparatus of claim 5 wherein the finite state machine includes a counterto control activation or deactivation of individual ones of theimpedance-generation devices based on a shift of the reference impedancecode.
 7. The apparatus of claim 1 wherein the circuit attributes includeon-die termination, input/output pre-driver strength, timing control,slew rate, or signal edge rate control.
 8. The apparatus of claim 1,further comprising a comparator circuit coupled to the single externalimpedance element and to the plurality of impedance-generation devicescoupled to the single external impedance element, the comparator circuithaving an output terminal coupled to the control circuit to provide thecontrol circuit with a signal to generate the reference impedance codeif the at least one device activated by the control circuit generatesthe impedance that substantially matches the impedance of the singleexternal impedance element.
 9. The apparatus of claim 1 wherein theimpedance-generation devices comprise transistors having differentwidths that correspond to a different impedance generated by eachtransistor, and wherein a shift in the reference impedance code by thecontrol circuit results in activation or deactivation of transistors togenerate different impedances related to an amount of the shift.
 10. Anapparatus, comprising: a single external resistor having a resistance; afirst plurality of transistors coupled to the single external resistor;a control circuit coupled to the first plurality of transistors, thecontrol circuit capable to produce a reference resistance codecorresponding to a substantial match of the resistance of the singleexternal resistor based on a number of activated transistors in thefirst plurality of transistors; and at least a second plurality oftransistors coupled to the control circuit, the control circuit capableto activate or deactivate at least one transistor in the secondplurality of transistors based on the reference resistance code togenerate a resistance associated with a circuit attribute different froma circuit attribute associated with the first plurality of transistors.11. The apparatus of claim 10 wherein the control circuit comprises afinite state machine having a counter to control activation ofindividual transistors of the second plurality of transistors based on ashift of the reference resistance code.
 12. The apparatus of claim 10wherein the second plurality of transistors comprise transistors havingdifferent widths that correspond to a different resistance generated byeach transistor, and wherein a shift in the reference resistance code bythe control circuit results in activation or deactivation of transistorsto generate different resistances related to an amount of the shift. 13.The apparatus of claim 10 wherein the transistors of the first or secondplurality of transistors comprise P-channel transistors.
 14. A system,comprising: a single external resistor having a resistance and mountedon a motherboard; a first plurality of transistors on a chip and coupledto the single external resistor by a pad or pin, the first plurality oftransistors being associated to a first circuit attribute; a controlcircuit on the chip and coupled to the first plurality of transistors,the control circuit capable to produce a reference resistance codecorresponding to a substantial match of the resistance of the singleexternal resistor based on a number of activated transistors in thefirst plurality of transistors; and at least a second plurality oftransistors on the chip and coupled to the control circuit, the controlcircuit capable to activate or deactivate at least one transistor in thesecond plurality of transistors based on a shift of the referenceresistance code to generate a resistance associated with a secondcircuit attribute different from the first circuit attribute associatedwith the first plurality of transistors.
 15. The system of claim 14wherein the transistors comprise P-channel transistors, N-channeltransistors, or a combination of P-channel transistors and N-channeltransistors.
 16. The system of claim 14, further comprising a bus thatcouples the chip to a processor mounted on the motherboard via anotherpad, wherein the circuit attribute associated with the first pluralityof transistors is related to an impedance of the bus.
 17. The system ofclaim 14 wherein the second plurality of transistors comprisetransistors having different widths that correspond to a differentresistance generated by each transistor, and wherein the shift in thereference resistance code by the control circuit results in activationor deactivation of transistors to generate different resistances relatedto an amount of the shift.
 18. The system of claim 14 wherein thecontrol circuit comprises a finite state machine having a counter tocontrol activation of individual transistors of the second plurality oftransistors based on the shift of the reference resistance code.
 19. Thesystem of claim 14, further comprising a machine-readable medium havinginstructions stored thereon to control operation of the control circuitto activate or deactivate at least one transistor in the secondplurality of transistors based on the shift of the reference resistancecode, in response to a state of the second circuit attribute.
 20. Amethod, comprising: activating at least one of a first plurality ofimpedance-generation devices associated to a first circuit attribute,until an impedance of the activated impedance-generation devicessubstantially matches an impedance of a single external impedanceelement; based on a number of the activated impedance-generationdevices, generating a reference impedance code corresponding to theimpedance of the activated impedance-generation devices; shifting thereference impedance code; and using the shifted reference impedance codeto activate at least one of a second plurality of impedance-generationdevices to generate an impedance associated with a second circuitattribute different from the first circuit attribute associated with thefirst plurality of impedance-generation devices.
 21. The method of claim20 wherein the second plurality of impedance-generation devicescomprises transistors having different widths that correspond to adifferent resistance generated by each transistor, and wherein shiftingthe reference impedance code and using the shifted reference impedancecode to activate at least one of the second plurality of transistorsinclude generating different resistances based an amount of the shift.22. The method of claim 20, further comprising repeating the shifting ofthe reference impedance code and repeating the using of the shiftedreference impedance code to activate at least one of the secondplurality of impedance-generation devices to generate a new impedance,in response to a change in state of the second circuit attribute. 23.The method of claim 20 wherein shifting the reference impedance codeincludes incrementing or decrementing a counter.
 24. The method of claim20 wherein the impedance-generation devices comprise P-channeltransistors, N-channel transistors, or a combination of P-channeltransistors and N-channel transistors.
 25. The method of claim 20wherein shifting the reference impedance code includes generating a newimpedance code from the shifted reference impedance code, and whereinusing the shifted reference impedance code to activate at least one ofthe second plurality of impedance-generation devices includes providingthe new impedance code to a control circuit that activates at least oneof the second plurality of impedance-generation devices that correspondsto the new impedance code.
 26. An article of manufacture, comprising: amachine-readable medium having stored thereon instructions to: activateat least one of a first plurality of impedance-generation devicesassociated to a first circuit attribute, until an impedance of theactivated impedance-generation devices substantially matches animpedance of a single external impedance element; based on a number ofthe activated impedance-generation devices, generate a referenceimpedance code corresponding to the impedance of the activatedimpedance-generation devices; shift the reference impedance code; anduse the shifted reference impedance code to activate at least one of asecond plurality of impedance-generation devices to generate animpedance associated with a second circuit attribute different from thefirst circuit attribute associated with the first plurality oftransistors.
 27. The article of manufacture of claim 26 wherein theinstructions to shift the reference impedance code include instructionsto increment or decrement a counter.
 28. The article of manufacture ofclaim 26 wherein the second plurality of impedance-generation devicescomprises transistors having different widths that correspond to adifferent resistance generated by each transistor, and wherein theinstructions to shift the reference impedance code and to use theshifted reference impedance code to activate at least one of the secondplurality of transistors result in generation of different resistancesbased an amount of the shift.
 29. The article of manufacture of claim 26wherein the machine-readable medium further includes instructions storedthereon to repeat the shifting of the reference impedance code and torepeat the using of the shifted reference impedance code to activate atleast one of the second plurality of impedance-generation devices togenerate a new impedance, in response to a change in state of the secondcircuit attribute.
 30. The article of manufacture of claim 26 whereinthe instructions stored on the machine-readable medium are executable bya processor as part of a basic input/output system (BIOS) routine.